1. Field of the Invention
The present invention relates to a method for making a layer containing a magnetic material such as magnetic layers, and more particularly to a method for selectively removing a layer containing a magnetic material without using a mask pattern.
2. Description of the Related Art
Etching of a magnetic material contained layer will be explained with reference to FIG. 4.
As shown in FIG. 4A, a magnetic material contained layer 102 is formed on a substrate 101 to have a film thickness of about 1 .mu.m by a magnetron sputtering device. Thereafter, a resist is applied to the magnetic material contained layer 102, and lithograph and developing treatments are provided to the resist, thereby forming a resist pattern 103.
As shown in FIG. 4B, the resist pattern 103 is used as a mask, and the magnetic material contained layer 102 is etched by RIE (Reactive Ion Etching), thereby forming magnetic material contained layers 102a to 102c. The process conditions, are given as follows, an etching gas: SiCl.sub.4 /N.sub.2 /Cl.sub.2 /NH.sub.3, and a temperature: about 250.degree. C. At this case, since the magnetic material contained layer 102 is composed of a difficult-etch material, a selection ratio of the magnetic material contained layer 102 to the resist pattern 103 is 1 or less. Therefore, the resist pattern 103 is etched at the same time when the magnetic material contained layer 102 is etched. As a result, the film thickness of the resist pattern 103 is largely thinned.
Then, as shown in FIG. 4C, the resist pattern 103 is removed by ashing or a resist release agent.
As mentioned above, the magnetic material contained layer 102 is etched with the resist pattern 103 serving as a mask. In this time, since the selection ratio is 1 or less, it is required that the thickness of the resist pattern 103 be formed about ten times that of the magnetic material contained layer 102. However, if the thickness of the resist pattern 103 is set to 10 .mu.m, the resist pattern 103 is not sufficiently exposed in a direction of the thickness, and there is a case that a resist pattern 103a is left on a predetermined etching area (FIG. 5).
Furthermore, when the magnetic material contained layer 102 is etched with the resist pattern 103 including the resist pattern 103a serving as a mask, there is a case that etching residual 102' is generated. First, the resist pattern 103a and the resist pattern 103 are etched. Sequentially, the residual resist pattern 103 is used as a mask, and the magnetic material contained layer 102 is etched. At this time, the resist pattern 103 and the magnetic material contained layer 102 are simultaneously etched, the film thickness of the resist pattern 103 becoming thinner than the film thickness which is originally necessary for the mask. As a result, the resist pattern 103 does not serve as a mask, and the etching residual 102' is generated.
Moreover, the resist pattern 103 is etched not only in the up and down direction but also in the right and left direction. Due to this, as shown in FIG. 4C, the magnetic material contained layers 102a to 102c are formed in a tapering shape. The length L.sub.1 between upper portions of adjacent magnetic material contained layers 102a and 102b is 4.1 .mu.m, and the length L.sub.2 between bottom portions of adjacent magnetic material contained layers 102a and 102b is 2.5 .mu.m. An etching anisotropy is extremely bad.
By the way, for forming a semiconductor device, a planarization technique of an interlevel insulator is important. As a circuit element formed on a semiconductor substrate is made fine, the surface becomes uneven. Due to this, in forming a multilevel wiring layer, it is needed that breaking of wire at the uneven portion be reduced. As one of the planarization techniques, there is an etch back method.
The etch back method will be explained with reference to FIG. 7. A conductive layer 113 is formed on an insulating film 112 formed on a semiconductor substrate 111. Thereafter, an interlevel insulator 114 is formed on the entire surface. Thereafter, resist 115 is applied on the entire surface to smooth the surface (FIG. 7A).
By use of plasma etching, the resist 115 and the interlevel insulator 114 are etched. At this time, etching conditions are set such that the etching speed of resist 115 and that of the interlevel insulator 114 are the same. For example, as an etching gas, mixed gas of F gas and O.sub.2 gas is used. First, the resist 115 is evenly etched, and a projected portion of the interlevel insulator 114 is exposed (FIG. 7B).
Then, the interlevel insulator 114 and the resist 115 are simultaneously etched. At this time, when the interlevel insulator 114 is etched, O.sub.2 gas is generated. Due to this, a ratio of the etching gas changes. As a result, as compared with the interlevel insulator 114, the etching speed of the resist 115 becomes fast, a difference in level is generated on the surface of the etched interlevel insulator 114 (FIG. 7C).
As mentioned above, even in a case that the selection ratio of the resist 115 and the interlevel insulator 114 as such is set to be the same, the substantial selection ratio is changed by the conductive pattern, that is, the shape of the interlevel insulator 114. Due to this, it is difficult to set suitable etching conditions.
Also, as shown in FIG. 8, if adjacent conductive layers 113 are formed in a separating shape, there is a case that resist 115 is little applied on the projected portion of the interlevel insulator 114. In this case, as compared with the case of FIG. 7, the ratio of etching gas is largely changed, the difference in level on the surface of the etched interlevel insulator 114 is increased.
As mentioned above, in the etching method of the magnetic material contained layer, since the magnetic material contained layer as such is composed of the difficult-etch material, the selectivity between the magnetic material contained layer and the etching mask worsens, and it is difficult for the magnetic material contained layer to be formed to a predetermined size.
Moreover, if there is a difference in level on the interlevel insulator after the interlevel insulator on the semiconductor substrate is etched, there is a case that breaking of wire occurs in the conductive layer formed on the interlevel insulator. Due to this, it is needed that the interlevel insulator be further planarized. However, since the etching condition differs for every conductive pattern, and the conductive pattern differs every type, it is difficult for the etching condition to be suitably set.